Are you on board with this round of digital currency surge?

 　Early 2020

　　If a person were to invest in bitcoin

　　I'm afraid few people would do so

　　The inherent risk and uncertainty

　　that many people would shy away from

　　However, if you were to ask again today

　　I'm afraid the "no" would be a "regret".

　　As bitcoin began its surge in late 2020

　　many people began to rush to the market

　　And the mining market behind it has become

　　A "machine" is hard to find

　　And the most sought-after "meat and potatoes"

　　The most sought-after "meat and potatoes" is the AMD CPU-equipped mining machine

　　What is the reason behind this?

　　

　　The dazzling jewel in the king's crown

　　With the recent expansion of Filecoin's mining servers, AMD CPUs have become the meat and potatoes, with Filecoin's Proof of Replication (PoRep) tending to run on AMD processors. There are actually multiple architectures of CPUs available for IPFS tasks, including X86, ARM and several other reliable vendors, in addition to GPU architectures to choose from. Still, the vast majority of systems in the space today are powered by AMD CPUs (and sometimes Nvidia GPUs) for arithmetic.

　　Not surprisingly, this is due to the rise of the "Rome" (AMD's second-generation EPYC processor codenamed Rome, aka "Rome"), whose impressive price/performance ratio was undoubtedly the key to the choice of IPFS systems. "The Rome processor is the world's first 7nm high-performance x86 CPU, with an average IPC improvement of 15% for a single thread and 23% for 32 cores and 64 threads, making it the king of price/performance.

　　

　　One of the biggest drawbacks of AMD's first generation EPYC processors (codenamed Naples, a.k.a. "Naples") was their complexity. AMD built its 32-core Naples processors by enabling four 8-core silicon chips and connecting each chip to two storage channels, which resulted in an uneven storage structure (NUMA).

　　This "quad-NUMA" architecture causes many NUMA balancing problems in many applications. Since this problem exists in almost every operating system, reports claim that this has resulted in system administrators having to do a lot of optimization work in some cases to get the best performance out of the EPYC 7001 series.

　　AMD's second-generation EPYC Rome processors have cleverly addressed this issue. The central processor design implements a central input-output hub through which all off-chip communications are routed. The complete design uses eight core small chips, called core composite chips (CCDs); a central chip for input/output, called input/output chips (IODs).

　　All CCDs communicate with this central I/O center via a dedicated high-speed infinite fiber (IF) link, through which the core can communicate with internal DRAM and PCIe channels or other cores.

　　The CCD consists of two quad-core core complexes (1 CCD = 2 CCXs). Each CCX consists of four cores and 16mb L3 cache, located in the center of the "Rome". The top 64-core Rome processor has a total of 16 CCXs, and those CCX processors can only communicate with each other through the central input and output chips. There is no chip CCD communication.

　　

　　In the picture above, on the left is the first generation EPYC Naples processor chip, using four Zepellin dies, each connected to the other with an IF link. On the right is the second generation EPYC Rome processor chip with eight green CCDs on the outside and a central IO Die in the middle with DDR and PCIe interfaces.

　　

　　With an unprecedented number of cores and the ultimate pursuit of performance, AMD's second-generation EPYC Rome processor has taken over the market and become one of the most eye-catching gems in the crown of AMD, the king of the industry.

　　How "Rome" was built

　　The AMD Infinity (IF bus multi-core package design) architecture used in the second-generation EPYC Rome servers is a hybrid multi-chip architecture that has reached new heights in the AMD EPYC (Skylar) family of processors. In fact, the AMD Infinity architecture is now divided into two main parts: eight chips as processor cores and one I/O chip for processor security and external communication.

　　The main advantage of the second-generation "EPYC 7002" family over the first-generation EPYC Naples processors is that they are easier to understand and optimize. Each processor has only one memory latency environment, as each core talks to all eight memory channels at the same time with the same latency. Compared to the first generation of EPYC Naples processors with 3 NUMA environments, the second generation "EPYC 7002" series is directly connected to memory with only 2 NUMA regions per CPU.

　　This flexible design not only allows the CPU cores to use advanced manufacturing processes, but also allows the I/O circuitry to evolve on its own, and because of this non-integrated chip design, users can bring new products to market faster with EPYC. new capabilities of the server.

　　As for I/O interfaces, AMD's second-generation EPYC Rome processors support the PCIe 4.0 standard while enabling enterprises to build 128 lanes of I/O, doubling network broadband performance.

　　Die interconnection is Infinity Fabric on Package, or IFOP for short; bit width is 32bit; 1 clock does 4 transfers and runs on memory frequency, for DDR4@2666MHz speaking, running on 1333MHz, then the one-way bandwidth is 4*1333MHz*32bit/8/ 1000=21.328GB/s and bidirectional bandwidth is 2*21.328GB/s=42.656GB/s.

　　With all 4 xGMIs used for interconnect, a dual-lane system does provide 128 PCI-E 4.0 lanes as a single-lane system; however, if the motherboard manufacturer only uses 3 xGMI lanes for interconnect, then each processor will also free up bandwidth equivalent to 16 PCI-E 4.0 lanes (two processors will provide 32 more PCI-E 4.0 lanes) This increases the number of PCI-E 4.0 lanes in a dual-lane system to 160 (with the two additional PCI-E 2.0 lanes provided by the system, the entire dual-lane system can provide up to 162 PCI-E lanes).

　　

　　

　　The new AMD servers typically have three x16 PCIE Gen4 links, for a total unidirectional bandwidth of 31.51 x 3 = 94.5 GB/s bandwidth.

　　Such high bandwidth enables better performance for high data throughput devices, meeting the demanding computing and storage requirements of applications such as high performance computing, artificial intelligence, cloud computing and enterprise data centers.

　　With leading-edge performance and innovative features, AMD's second-generation EPYC processors set a new benchmark for modern data center processors and have won widespread support from partners including Dell EaseUS.

　　Two swords in one.

　　Dell EaseUS + AMD EPYC

　　As a leader in modern infrastructure, Dell Secure understands that enterprises demand multi-cloud agility and want the right workloads paired with the ideal IT infrastructure. Servers are an important cornerstone of a modern data center, and based on the advantages of AMD EPYC's more cores, 8-channel memory and PCIE bandwidth, Dell EaseUS has partnered with AMD to launch high-performance servers with second-generation EPYC processors.

　　It includes: single-way Dell EaseUS PowerEdge Server R6515 and R7515, dual-way Dell EaseUS PowerEdge Server R6525 and R7525, compute-intensive Dell EaseUS PowerEdge Server C6525 (2U 4-node), and hyper-converged infrastructure VxRail E665, E665F, E665N.

　　Let's start with a family photo of Dell EaseUS AMD EPYC.

　　

　　

　　Based on AMD's second-generation EPYC processors, Dell EaseUS PowerEdge servers deliver the computing performance, manageability and integrated security users need for multi-cloud environments and a variety of emerging workloads.

　　01

　　Improved Performance

　　- A 100 percent increase in the number of processor cores for faster data transfers.

　　- A 20 percent increase in memory speed for reduced latency and improved responsiveness.

　　- PCIe Gen4 speeds up to 16 GT/s, doubling performance over previous generations and breaking through bottlenecks in one fell swoop.

　　02

　　Easy Management

　　- Reduce deployment time by up to 96% with the OpenManage system management solution.

　　- Easy BIOS tuning through server profiles optimized for workloads.

　　- 56% improvement in data center cooling power utilization efficiency (PUE).

　　03

　　Integrated end-to-end security

　　- Protecting data at rest with OpenManage Secure Enterprise Key Manager and AMD Secure Memory Encryption.

　　- Maintaining enterprise-wide security through automated firmware and compliance deviation detection with iDRAC and OpenManage Enterprise.

　　- Providing 509 unique keys through secure encryption virtualization.

　　In addition, Dell EaseUS PowerEdge servers with AMD's second-generation EPYC processors, all with Rome processors paired with Rome motherboards, are capable of delivering the best performance of AMD EPYC chips. It is fully optimized for price/performance in virtualization, software-defined storage, data analytics, high-performance computing and other workloads.

　　As enterprises demand more computing power and demand more total cost of ownership for servers, Dell EaseUS' PowerEdge series servers based on AMD's second-generation EPYC processors will reshape the cornerstone of the entire data center and help enterprises better meet the challenges of the multi-cloud era.